HW-SW Codesign

Beyond Exascale: Dataflow Domain Translation on a Cerebras Cluster
Tomas Oppelstrup, Nicholas Giamblanco, Delyan Z Kalchev, Ilya Sharapov, Mark Taylor, Dirk Van Essendelft, Sivasankaran Rajamanickam, Michael James
Cello: Co-Designing Schedule and Hybrid Implicit/Explicit Buffer for Complex Tensor Reuse
Raveesh Garg, Michael Pellauer, Sivasankaran Rajamanickam, Tushar Krishna
Breaking the Molecular Dynamics Timescale Barrier Using a Wafer-Scale System
Kylee Santos, Stan Moore, Tomas Oppelstrup, Amirali Sharifian, Ilya Sharapov, Aidan Thompson, Delyan Z Kalchev, Danny Perez, Robert Schreiber, Scott Pakin, Edgar a Leon, James H Laros III, Michael James, Sivasankaran Rajamanickam
Batched Linear Solvers in Kokkos Kernels
Mar 2, 2023 12:00 AM Amsterdam, Netherlands.
Scientific Machine Learning and Data flow acceleration: ASCR HQ Update
Mar 1, 2023 12:00 AM Albuquerque
Recent Experiences on Accelerating Machine Learning Workloads on SambaNova Systems
Feb 3, 2023 12:00 AM Atlanta
Accelerating Selected DOE Machine Learning Workloads on SambaNova Systems
Nov 15, 2022 12:00 AM Dallas
Understanding the design-space of sparse/dense multiphase GNN dataflows on spatial accelerators
Raveesh Garg, Eric Qin, Francisco Munoz-Martinez, Robert Guirado, Akshay Jain, Sergi Abadal, Jose Abellan, Manuel Acacio, Eduard Alarcon, Sivasankaran Rajamanickam, Tushar Krishna
Co-design of Data flow style Accelerators
Jun 26, 2022 12:00 AM Livermore, California.
Co-Designing Data Flow Accelerators
Feb 25, 2022 2:35 PM — 2:55 PM Online
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity
Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, Tushar Krishna
Codesign of Algorithms and Architectures

As architectures evolve from one generation to the next and when new paradigms such as data flow emerge, there are lots of opportunities to not just develop new algorithms for these architectures but to co-design both architectures and algorithms to realize gains that are otherwise not possible.
Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication
Gordon Moon, Hyoukjun Kwon, Geonhwa Jeong, Prashanth Chatarasi, Sivasankaran Rajamanickam, Tushar Krishna
Extending Sparse Tensor Accelerators to Support Multiple Compression Formats
Eric Qin, Geonhwa Jeong, William Won, Sheng-Chun Kao, Hyoukjun Kwon, Sudarshan Srinivasan, Dipankar Das, Gordon E Moon, Sivasankaran Rajamanickam, Tushar Krishna
Convergence of Special Purpose Accelerators and Traditional High Performance Computing
Feb 18, 2021 12:00 PM — 1:00 PM Online
Extending Sparse Tensor Accelerators to Support Multiple Compression Formats
Eric Qin, Geonhwa Jeong, William Won, Sheng-Chun Kao, Hyoukjun Kwon, Sudarshan Srinivasan, Dipankar Das, Gordon E Moon, Sivasankaran Rajamanickam, Tushar Krishna
Union: A unified HW-SW Co-Design ecosystem in MLIR for evaluating tensor operations on spatial accelerators
Geonhwa Jeong, Gokcen Kestor, Prasanth Chatarasi, Angshuman Parashar, Po-an Tsai, Sivasankaran Rajamanickam, Roberto Gioiosa, Tushar Krishna
Towards simulations on the Exascale hardware and beyond
Dec 3, 2020 3:30 PM — 5:00 PM University of Texas, Austin.
Recent Experiences with Machine Learning: Perspectives from Algorithms, Architectures and Applications
Aug 3, 2020 1:10 PM — 1:50 PM Online.
Designing vector-friendly compact BLAS and LAPACK kernels
Kyungjoo Kim, Timothy B Costa, Mehmet Deveci, Andrew M Bradley, Simon D Hammond, Murat E Guney, Sarah Knepper, Shane Story, Sivasankaran Rajamanickam