HW-SW Codesign

Breaking the Molecular Dynamics Timescale Barrier Using a Wafer-Scale System
Batched Linear Solvers in Kokkos Kernels
Understanding the design-space of sparse/dense multiphase GNN dataflows on spatial accelerators
Co-design of Data flow style Accelerators
Co-Designing Data Flow Accelerators
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity
Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication
Extending Sparse Tensor Accelerators to Support Multiple Compression Formats
Extending Sparse Tensor Accelerators to Support Multiple Compression Formats
Union: A unified HW-SW Co-Design ecosystem in MLIR for evaluating tensor operations on spatial accelerators
Towards simulations on the Exascale hardware and beyond
Designing vector-friendly compact BLAS and LAPACK kernels